1. Field of the Invention
The present invention relates to a PLL (phase locked loop) using a lock detecting circuit, and more particularly, to an improved PLL using a lock detecting circuit capable of decreasing the delay of jitter noise and locked-in time serving as two characteristics of PLL trade-off, thereby decreasing chip area with a simplified logic circuit of the lock detecting circuit without using an additional phase detection.
2. Description of the Background Art
FIG. 1 is a block diagram illustrating a conventional PLL circuit. As shown therein, the PLL includes a main phase detector 1 detecting the phase of an input signal IN, a loop filter 2 receiving an output signal sinxcex8e of the main phase detector 1 and decreasing a noise bandwidth or shortening a locked-in time, a lock indicator 3 receiving the input signal IN and outputting an output signal to the loop filter 2, and a voltage controlled oscillator (VCO) 4 feeding back the output of the loop filter 2 to the phase detector 1 and the lock indicator 3.
The lock indicator 3 includes a phase converter 3-1 converting the phase of the output signal of the voltage controller oscillator 4 by 90xc2x0, a quad phase detector 3-2 converting the input signal IN and the output of the phase converter 3-1 to a cosine signal cosxcex8e, and a smoothing filter 3-3 smoothing the output of the quad phase detector 3-2.
FIG. 2 is a circuit view detailing the loop filter 2 in FIG. 1. As shown therein, the loop filter 2 includes a low resistor LR having a low resistance value and a high resistor HR having a high resistance value wherein the output of the phase detector 1 is applied to each terminal thereof, a three-phase switch SW controlled by the output signal of the smoothing filter 3-3 in the lock indicator 3 and selectively connected to the other terminals of the resistors LR, HR, and a capacitor C connected between the output terminal of the three-phase switch SW and the ground voltage.
The operation of the thusly constituted conventional PLL will now be described with reference to the accompanying drawings.
First, when the input signal IN is applied to the PLL, the main phase detector 1 detects the phase of the input signal IN and outputs the sine signal sinxcex8e to the loop filter 2.
At this time, the input signal IN is applied to the quad phase detector 3-2 of the lock indicator 3 which then outputs the cosine signal cosxcex8e to the smoothing filter 3-3.
Accordingly, when the PLL is locked, xcex8e of the cosine signal cosxcex8e of the quad phase detector 3-2 becomes 0xc2x0 so that the cosine output cosxcex8e becomes 1. That is, since the cosine output becomes 1, the three-phase switch SW of the loop filter 2 is connected to the high resistance HR in accordance with the output of the smoothing filter 3-3.
To the contrary, when the PLL is not locked, xcex8e of the cosine signal cosxcex8e 3-2 becomes 90xc2x0 so that the cosine output cosxcex8e becomes 0. That is, since the cosine output becomes 0, the three-phase switch SW of the loop filter 2 is connected to the low resistor LR in accordance with the output of the smoothing filter 3-3.
More specifically, the smaller the noise bandwidth of the PLL, the better becomes the signal-to-noise ratio (SNR), and accordingly when the PLL is not locked the three-phase switch SW of the loop filter 2 is connected to the low resistor LR so as to decrease the noise bandwidth. When locked, the three-phase switch SW should be connected to the high resistor so as to shorten the locked-in time.
However, the conventional PLL additionally requires the quad phase detector 3-2 for controlling such a switching operation, thereby disadvantageously increasing the chip area.
The present invention is directed to overcoming disadvantages of the conventional PLL.
Therefore, it is an object of the present invention to provide a PLL using a lock detecting circuit capable of shortening a locked-in time while decreasing a chip area, thereby improving noise characteristics.
To achieve the above-described object, there is provided a PLL using a lock detecting circuit according to the present invention which includes a phase frequency detector detecting the phase of an input signal and outputting an up signal and a down signal, a lock detecting circuit detecting whether the PLL is locked using the up and down signals, a charge pump pumping the up signal and the down signal, first and second voltage dividers respectively receiving the output signal of the charge pump, first and second switching means controlling the output signals of the first and second voltage dividers using the output signal of the lock detecting circuit and selectively outputting the result values, a capacitor connected between an output terminal connected in common to the first and second switching means and ground voltage, and a voltage controlled oscillator feeding back the output signals of the first and second switching means to the phase frequency detector.
The features and advantages of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific example, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.